The present invention relates to a semiconductor memory such as a large capacity dynamic RAM (Random Access Memory) provided with a multibit parallel test mode and to a technique especially effective in testing the function thereof.
With rapid progress in the use of large capacity dynamic RAMs, so-called multibit parallel testing (multibit testing) for use in simultaneously writing, reading, comparing and collating stored multibit data by gaining an access to a memory once has become defined by the JEDEC (Joint Electron Device Engineering Council) as means for increasing the efficiency of function testing. In such a dynamic RAM, a multibit parallel test mode is established when a WCBR (WE.multidot.CAS BEFORE RAS) cycle, for instance, is executed and the multibit parallel test mode is released when a CBR (CAS BEFORE RAS) or RAS only refresh cycle is executed. The WCBR cycle has already been referred to in U.S. Pat. No. 4,811,299.
The multibit parallel test mode, and the setting and resetting of that mode of the dynamic RAM or the like have also been described in the "Nikkei Micro Device," pp 53.about.62, for May, 1987, published by Nikkei MacGraw-Hill Co.
The number of parallel bits of stored data that can simultaneously be read, compared and collated in the above-mentioned conventional multibit parallel test mode is 8 for a 4 mega (1 mega means raising 2 to the 20th power) dynamic RAM and 16 for a 16 mega dynamic RAM, for instance. This signifies that while the storage capacity of the dynamic RAM is quadrupled, the number of parallel bits in the multibit parallel test mode is only doubled. This results in increasing the time required to test the functions of the larger dynamic RAM and the like.